The power output to Inductive loads such as Motors is commonly applied by using the well-known technique of Pulse Width Modulation (PWM). This technique is well explained in chapter 5 of the text “Power Electronics”, by Joseph Vithayathil, McGraw Hill Series in Electrical and Computer Engineering.
In a system using the PWM technique, voltage is applied to one or several points of the load by means of two switching devices such as transistors, or more precisely IGBTs (Insulated Gate Bipolar Transistors), in a bridge arrangement. One Switching device is connected from the positive pole of the power supply to the load, and the other one from the negative pole of the same power supply to the same load connection.
An inherent problem related to the PWM technique, is the introduction of a so-called Dead Time delay. This delay is introduced between the opening of one switch and the closing of the other switch. Such a delay is commonly introduced in order to avoid the possibility that the two switches will be activated together. Should both switches be activated together, then the power supply would be shorted and the high current would cause the destruction of the switches or of the power supply. Also, the switching time of the switching devices has some finite value, and that value may vary under different conditions, like temperature, load current, etc. Therefore, the Dead Time delay should have a higher value than the maximum switching time delay.
During the Dead Time delay, both switches are non-conducting. As a result, the voltage set on the load connection depends on the load condition, and in particular on the load current direction. If the current is positive (flowing toward the load), then it will be flowing through the lower leg bridge diode, and the voltage will be almost equal to that of the negative pole of the power supply. If the current is negative (flowing from the load to the switches), then the current will be flowing through the upper leg bridge diode, and the voltage will be almost equal to that of the positive pole of the power supply. This situation creates a non-deterministic relation between PWM duty cycle and voltage applied, and large imprecision in voltage output is observed.
Another problem created by the Dead Time delay is that voltages having a pulse width smaller than the Dead Time, cannot be output. Thus a voltage value close to Negative or Positive Power supply line voltage, which have respectively, a small on-time or a small off-time pulse width, cannot be output, thus creating a discontinuity in the voltage close to the negative or positive power supply voltage output.
When designing a PWM system, the engineer must make a difficult evaluation of the Dead Time influence. Too short a Dead Time delay will reduce the reliability of the system, i.e. under some conditions a short circuit can be obtained, while too long a Dead Time delay will spoil the system performance.
Switching schemes have been described in prior art patents which compensate for the voltage imprecision, however they do not resolve the discontinuity of average voltage output when the desired output voltage is near zero or near the DC power supply voltage. In U.S. Pat. No. 5,930,132 to Watanabe et al., an electronic system is shown with the purpose of minimizing the dead time delay. In this patent, the dead time delay is not eliminated, but only minimized. In U.S. Pat. No. 5,859,770 to Takada et al., an electronic arrangement is used that comprises a P channel transistor in order to reduce to almost zero the dead time. P channel transistors have the disadvantage of being limited in their power rating, so that in most modern systems only N channel IGBT's are used at high power. Thus the Takada et al. patent is not advantageous for medium and high power systems.
Therefore, it would be desirable to provide a system in which the Dead Time delay will not influence the precision of the system, which is applicable for the Power switching transistors commonly used today.